1 radiation hardened ultra low noise, precision voltage reference ISL71090SEH12 the ISL71090SEH12 is an ultra low noise, high dc accuracy precision voltage reference with a wide input voltage range from 4v to 30v. the ISL71090SEH12 uses the intersil advanced bipolar technology to achieve sub 2v p-p noise at 0.1hz with an accuracy over temperature and radiation of 0.15%. the ISL71090SEH12 offers a 1.25v output voltage with 10ppm/c temperature coefficient and also provides excellent line and load regulation . the device is offered in an 8 ld flatpack package. the ISL71090SEH12 is ideal fo r high-end instrumentation, data acquisition and applications requiring high dc precision where low noise performance is critical. applications ? rh voltage regulators precision outputs ? precision voltage sources for data acquisition system for space applications ? strain and pressure gaug e for space applications features ? reference output voltage . . . . . . . . . . . . . . . . . 1.25v 0.05% ? accuracy over temperature and radiation . . . . . . . . . .0.15% ? output voltage noise . . . . . . . . . . 1v p-p typ (0.1hz to 10hz) ? supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930a (typ) ? tempco (box method) . . . . . . . . . . . . . . . . . . . 10ppm/c max ? output current capability . . . . . . . . . . . . . . . . . . . . . . . . 20ma ? line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8ppm/v ? load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ppm/ma ? operating temperature range. . . . . . . . . . . .-55c to +125c ? radiation environment - high dose rate (50-300rad(si)/s) . . . . . . . . . . . 100krad(si) - low dose rate (0.01rad(si)/s) . . . . . . . . . . . . . 100krad(si)* - set/sel/seb . . . . . . . . . . . . . . . . . . . . . . . . 86mev ? cm 2 /mg *product capability established by initial characterization. the ?eh? version is acceptance tested on a wafer by wafer basis to 50krad(si) at low dose rate ? electrically screened to smd 5962-13211 related literature ? an1862, ?ISL71090SEH12 evaluation board user?s guide? ? an1863, ?see testing of the ISL71090SEH12? ? an1864, ?radiation report of the ISL71090SEH12? figure 1. ISL71090SEH12 typical application diagram figure 2. v out vs temperature 0.1f vee vdd refin vdd bipoff vee dacout gnd vin vref 1f d0 hs-565brh 1 2 3 4 6 8 7 5 ISL71090SEH12 d12 1.1k c note: select c to minimize settling time. dnc vin comp gnd dnc dnc vout trim 1.2500 1.2505 1.2510 1.2515 1.2520 1.2525 1.2530 -60 -40 -20 0 20 40 60 80 100 120 temperature (c) unit2 unit3 unit4 unit5 v out (v) unit1 june 26, 2013 fn8452.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL71090SEH12 2 fn8452.0 june 26, 2013 pin configuration ISL71090SEH12 (8 ld flatpack) top view ordering information ordering number (notes 1, 2, 3) part number v out option (v) temp range (c) package tape & reel (pb-free) pkg. dwg. # 5962r1321101vxc isl71090sehvf12 1.25 -55 to +125 8 ld flatpack k8.a isl71090sehf12/proto isl71090sehf12/proto 1.25 -55 to +125 8 ld flatpack k8.a isl71090sehf12eval1z evaluation board notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and c ompatible with both snpb and pb-free soldering operations. 2. for moisture sensitivity level (msl), please see device information page for ISL71090SEH12 . for more information on msl please see tech brief tb363 3. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbe rs listed in this ?ordering information? table must be used when ordering. 8 7 6 5 2 3 4 1 dnc vin comp gnd dnc dnc vout trim pin descriptions pin number pin name esd circuit description 1, 7, 8 dnc 3 do not connect. internally terminated. 2 vin 1 input voltage connection 3 comp 2 compensation and noise reduction capacitor 4 gnd 1 ground connection. also connected to the lid. 5 trim 2 voltage reference trim input 6 vout 2 voltage reference output vdd capacitively triggered clamp gnd vdd gnd pin esd circuit 1 esd circuit 2 esd circuit 3 vdd dnc
ISL71090SEH12 3 fn8452.0 june 26, 2013 functional block diagram comp gnd vout trim dnc dnc dnc band gap reference bias regulator vin gm 1.2v 1.2v 3.7v
ISL71090SEH12 4 fn8452.0 june 26, 2013 absolute maximum rating s thermal information max voltage v in to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +40v v in to gnd at an let = 86mev ? cm 2 /mg . . . . . . . . . . . . . . -0.5v to +36v v out to gnd (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v out + 0.5v voltage on any pin to ground . . . . . . . . . . . . . . . . . -0.5v to +v out + 0.5v voltage on dnc pins . . . . . . . . . . . . no connections permitted to these pins esd ratings human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750v thermal resistance (typical) ja (c/w) jc (c/w) 8 ld flatpack package (notes 4, 5). . . . . . 140 15 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c maximum junction temperature (t jmax ). . . . . . . . . . . . . . . . . . . . . .+150c pb-free reflow profile (note 6). . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0v to +30v temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the "case temp" location is the center of the ceramic on the package underside. 6. post-reflow drift for the ISL71090SEH12 devices can be 100v ty pical based on experimental results with devices on fr4 double sided boards. the engineer must take this into account when considering the reference voltage after assembly. 7. product capability established by initial characterization. the "eh" version is acceptance tested on a wafer by wafer basis t o 50krad(si) at low dose rate. 8. the output capacitance used for see testing is c in = 0.1f and c out = 1f. electrical specifications v in = 5v, i out = 0, c l = 0.1f and c c = 0.01f unless otherwise specified. boldface limits apply over the operating temperature range, -55c to +125c. parameter description conditions min (note 9) typ max (note 9) unit v out output voltage v in = 5v 1.252 v v oa v out accuracy @ t a = +25c (note 6) v out = 1.25v -0.05 +0.05 % v oa v out accuracy @ t a = -55c to +125c v out = 1.25v -0.15 +0.15 % tc v out output voltage temperature coefficient (note 11) 10 ppm/c v in input voltage range (note 10) v out = 1.25v 4.0 30 v i in supply current 0.930 1.28 ma v out / v in line regulation v in = 4.0v to 30v, v out = 1.25v 8 18 ppm/v v out / i out load regulation sourcing: 0ma i out 20ma 35 55 ppm/ma v d dropout voltage (note 10) v out = 1.25v @ 10ma 1.7 2.25 v i sc+ short circuit current t a = +25c, v out tied to gnd 53 ma i sc- short circuit current t a = +25c, v out tied to v in -23 ma t r turn-on settling time 90% of final value, c l = 1.0f, c c = open 250 s psrr ripple rejection f = 120hz 90 db e n output voltage noise 0.1hz f 10hz, v out = 1.25v 1.0 v p-p v n broadband voltage noise 10hz f 1khz, v out = 1.25v 1.2 v rms noise density f = 1khz, v out = 1.25v, v in = 6v 21 nv/ hz v out / t long term drift t a = 125c, 1000hrs 15 ppm notes: 9. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 10. v in -v out measured at the point where v out drops 1mv from the nominal measured value. 11. over the specified temperature range. temperature coefficien t is measured by the box method whereby the change in v out(max) - v out(min) is divided by the temperature range; in this case, -55c to +125c = +180c. 12. dropout voltage is the minimum v in - v out differential voltage measured at the point where v out drops 1mv from v in = nominal at t a = +25c.
ISL71090SEH12 5 fn8452.0 june 26, 2013 typical performance curves v in = 5v, v out = 1.25v, t a = +25c, unless otherwise specified. figure 3. line regulation over temperature (0ma) figure 4. load re gulation over temperature at v in = 5v (ppm/ma) figure 5. v out vs v in at 0ma, 20ma and -10ma figure 6. dropout voltage for 1.25v fig ure 7. load transient (0ma to 1ma) -2 -1 0 1 2 3 4 line reg (ppm/v) line reg ppm/v +25c line reg ppm/v +125c line reg ppm/v -55c v in (v) 0 5 10 15 20 25 30 35 load reg (ppm/ma) i out (ma) -50 -40 -30 -20 -10 0 10 20 02468101214161820 load reg ppm/ma (v in = 5v +125c) load reg ppm/ma (v in = 5v +25c) load reg ppm/ma (v in = 5v -55c) 0 5 10 15 20 25 30 35 v in (v) v out (v) 1.2485 1.2490 1.2495 1.2500 1.2505 1.2510 1.2515 1.2520 v out (v) 0ma +25 c v out (v) 20ma +25 c v out (v) -10ma +25 c v out (v) 0ma +125 c v out (v) 20ma +125 c v out (v) -10ma +125 c v out (v) 0ma -55 c v out (v) 20ma -55 c v out (v) -10ma -55 c 0.5 1.0 1.5 2.0 2.5 3.0 0.005 0.010 0.015 0.020 0.025 0 0 dropout v at +25c dropout v at +125c dropout v at +150c i out (ma) dropout (v) time (s) -200 -40 -30 -20 -10 0 10 20 30 40 0 200 400 600 800 v out (mv) +25c v in = 5v, v out = 1.25v, i out = 0ma to 1ma to 0ma, comp = 1nf, c out = 1f, v/div = 20mv/div
ISL71090SEH12 6 fn8452.0 june 26, 2013 figure 8. turn-on settling time figure 9. typica l temperature coefficient plot for 5 units figure 10. noise density vs frequency (v in = 6v, rl = open) figure 11. psrr (+25 c , v in = 5v, v out = 1.25v, i out = 0ma, c in = 0.1f, c out = 1f, comp = 1nf, v sig = 300mv p-p ) typical performance curves v in = 5v, v out = 1.25v, t a = +25c, unless otherwise specified. (continued) v out 200mv/div v in 10v/div 50s/div 1.2500 1.2505 1.2510 1.2515 1.2520 1.2525 1.2530 -60 -40 -20 0 20 40 60 80 100 120 temperature (c) unit2 unit3 unit4 unit5 v out (v) unit1 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 0.1 1 10 100 1k 10k 100k n o i s e ( v / h z ) frequency (hz) f = 1khz, en = 21.02nv/ hz -120 -100 -80 -60 -40 -20 0 10 100 1k 10k 100k 1m psrr (db) frequency (hz)
ISL71090SEH12 7 fn8452.0 june 26, 2013 device operation bandgap precision reference the ISL71090SEH12 uses a bandgap architecture and special trimming circuitry to produce a temperature compensated, precision voltage reference with high input voltage capability and moderate output current drive. applications information board mounting considerations for applications requiring the hi ghest accuracy, board mounting location should be reviewed. the device uses a ceramic flatpack package. generally, mild stresses to the die when the printed circuit (pc) board is heated and cooled, can slightly change the shape. because of these die stresse s, placing the device in areas subject to slight twisting can cause degradation of reference voltage accuracy. it is normally be st to place the device near the edge of a board, or on the shortest side, because the axis of bending is most limited in that location. mounting the device in a cutout also minimizes flex. obvi ously, mounting the device on flexprint or extremely thin pc material will likewise cause loss of reference accuracy. board assembly considerations some pc board assembly prec autions are necessary. normal output voltage shifts of typically 100v can be expected with pb-free reflow profiles or wave solder on multi-layer fr4 pc boards. precautions should be ta ken to avoid excessive heat or extended exposure to high reflow or wave solder temperatures. noise performance and reduction the output noise voltage over th e 0.1hz to 10hz bandwidth is typically 2v p-p (v out = 1.25v). the noise measurement is made with a 9.9hz bandpass filter. noise in the 10hz to 1khz bandwidth is approximately 1.6v rms (v out = 1.25v), with 0.1f capacitance on the output. this noise measurement is made with a band pass filter of 990hz. load capacitance up to 10f (with comp) can be added but will result in only marginal improvements in output noise and transient response. turn-on time normal turn-on time is typically 250s, the circuit designer must take this into account when l ooking at power-up delays or sequencing. temperature coefficient the limits stated for temperature coefficient (tempco) are governed by the method of measurement. the overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures which provide for the maximum voltage deviation and take the total variation, (v high -v low ), this is then divided by the temperature extremes of measurement (t high ?t low ). the result is divided by the nominal reference voltage (at t = +25c) and multiplied by 10 6 to yield ppm/c. this is the ?box? method for specifying temperature coefficient. output voltage adjustment the output voltage can be adjusted above and below the factory-calibrated value via the trim terminal. the trim terminal is the negative feedback divider point of the output op amp. the positive input of the amplifier is about 1.216v, and in feedback, so will be the trim voltage. the suggested method to adjust the output is to connect a 1m ? external resistor directly to the trim terminal and connect the other end to the wiper of a potentiometer that has a 100k ? resistance and whose outer terminals connect to v out and ground. if a 1m ? resistor is connected to trim, the output adjust range will be 6.3mv. the trim pin should not have any capaci tor tied to its output, also it is important to minimize the capacitance on the trim terminal during layout to preserve output amplifier stability. it is also best to connect the series resistor directly to the trim terminal, to minimize that capacitance and also to minimize noise injection. small trim adjustments will not disturb the factory-set temperature coefficient of the re ference, but trimming near the extreme values can. output stage the output stage of the device has a push pull configuration with an high side pnp and a low side npn. this helps the device to act as a source and sink. the device can source 20ma. use of comp cap the reference can be compensated for the c out capacitors used by adding a capacitor from comp pin to gnd. see table 1 for recommended values. of the comp capacitor. see testing the device was tested under ion beam at an let of 86mev?cm 2 /mg. the device did not latch up or burn out to a vdd of 36v and at +125c. single event transients were observed and are summarized in the table 2: dnc pins these pins are for trimming purpose and for factory use only. do not connect these to the circuit in any way. it will adversely effect the performance of the reference. table 1. c out (f) c comp (nf) 0.1 1 11 10 10 table 2. v in (v) i out (ma) c out (f) set (% v out ) 4 5 1 -4.6 30 5 1 -4.4 30 5 10 -1.0
ISL71090SEH12 8 fn8452.0 june 26, 2013 package characteristics weight of packaged device 0. 31 grams (typical) lid characteristics finish: gold potential: connected to lead #4 (gnd) case isolation to any lead: 20 x 10 9 ? (min) die characteristics die dimensions 1464m x 1744m (58mils x 69mils) thickness: 483m 25m (19mils 1 mil) interface materials glassivation type: nitrox thickness: 15k? top metallization type: alcu (99.5%/0.5%) thickness: 30k? backside finish silicon assembly related information substrate potential floating additional information worst case current density <2 x 10 5 a/cm 2 process dielectrically isolated advanced bipolar technology- pr40 soi metallization mask layout gnd gnd powr quiet comp vs dnc dnc dnc vout sense vout force trim (see note 13, table 3)
ISL71090SEH12 9 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8452.0 june 26, 2013 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability table 3. die layout x-y coordinates pad name pin number x (m) y (m) bond wires per pad gnd pwr 4 -104 0 1 gnd quiet 4 0 0 1 comp 3 -108 589 1 vs 2 -125 1350 1 dnc 1 -108 1452 1 dnc 8 1089 1452 1 dnc 7 1089 1350 1 vout sense 6 1072 598 1 vout force 6 1088 1 1 trim 5 985 -25 1 notes: 13. origin of coordinates is the centroid of gnd quiet. 14. bond wire size is 1.0 mil. revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change june 26, 2013 fn8452.0 initial release.
ISL71090SEH12 10 fn8452.0 june 26, 2013 package outline drawing k8.a 8 lead ceramic metal seal flatpack package rev 3, 3/13 lead finish side view top view -d- -c- 0.265 (6.75) 0.110 (2.79) 0.026 (0.66) 0.265 (6.73) seating and 0.180 (4.57) 0.03 (0.76) min base plane -h- 0.009 (0.23) 0.005 (0.13) pin no. 1 id area 0.050 (1.27 bsc) 0.022 (0.56) 0.015 (0.38) min 0.245 (6.22) 0.087 (2.21) 0.170 (4.32) 0.370 (9.40) 0.325 (8.26) 0.004 (0.10) 0.245 (6.22) 1. adjacent to pin one and shall be loca ted within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab may be used to identify pin one. 2. of the tab dimension do not apply. 3. the maximum limits of lead dimensions (section a-a) shall be measured at the centroid of the fini shed lead surfaces, when solder dip or tin plate lead finish is applied. 4. 5. shall be molded to the bottom of the package to cover the leads. 6. meniscus) of the lead from the body. dimension minimum shall be reduced by 0.0015 inch (0. 038mm) maximum when solder dip lead finish is applied. 7. 8. notes: 0.015 (0.38) 0.008 (0.20) pin no. 1 id optional 1 2 4 6 3 dimensioning and tolerancing per ansi y14.5m - 1982. controlling dimension: inch. index area: a notch or a pin one identification mark shall be located if a pin one identification mark is used in addition to a tab, the limits measure dimension at all four corners. for bottom-brazed lead packages, no organic or polymeric materials dimension shall be measured at the point of exit (beyond the section a-a base metal 0.007 (0.18) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) max 0.022 (0.56) 0.015 (0.38) 0.036 (0.92)
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